The posts on this blog are arranged in a fashion, starting from the latest going down to the oldest
Showing posts with label digital logic design. Show all posts
Showing posts with label digital logic design. Show all posts

Friday, September 5, 2008

DLD practical write-ups

Hi friends,
This is Adarsh here.
1.Troubled with the completion of your journals?
2.Can't find write-ups?
3.Confused about he format to write-down your journal?

Don't worry. This won't go on any longer.
From now on I am going to post the links to the write-ups of DLD practicals conducted in our college (Y.T.I.E.T).
So keep checking this post for newer links.

Click on the titles to download

Experiment 1.To study logic gates

[Contributed by myself (Adarsh)]


Experiment 2.Implementation of EX-OR and EX-NOR using NAND and NOR gates

[Contributed by Viraj Gupte]

Experiment 3. Study of half adder , full adder, half subtractor, full subtractor, BCD adder
[Contributed by myself (Adarsh)]

Experiment 4.Implementations of logic equations using MUX and DEMUX
[Contributed by myself (Adarsh)]

Experiment 5.To study operation of decoder driver IC 7447 and to verify the truth table
[Contributed by myself (Adarsh)]

Experiment 6. Conversion of JK flip-flop to T and D flip-flop
[Contributed by myself (Adarsh)]

Experiment 7.To design and implement MOD 4 asynchronous counter using JK flip-
[Contributed by myself (Adarsh)]

Experiment 8.To study parity bit checker / generator
[Contributed by myself (Adarsh)]


Comments awaited.